LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164.ALL;
ENTITY xor2 IS
PORT ( a: IN STD_LOGIC;
b: IN STD_LOGIC;
y: OUT STD_LOGIC);
END xor2;
ARCHITECTURE behave OF xor2 IS
BEGIN
y＜=a XOR b;
END behave;
(2)用VHDL語言的數據流描述方式實現二輸入異或門的邏輯功能：
LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164.ALL;
ENTITY xor2 IS
PORT( a: IN STD_LOGIC;
b: IN STD_LOGIC;
y: OUT STD_LOGIC);
END xor2;
ARCHITECTURE dataflow OF xor2 IS
BEGIN
PROCESS(a，b)
VARIABLE comb: STD_LOGIc_VECTOR(1 DOWNTO 0);
BEGIN
comb: =a&b;
CASE comb IS
WHEN "00"=＞y＜='0';
WHEN "01"=＞y＜='1';
WHEN "10"=＞y＜='1';
WHEN "11"=＞y＜='0';
WHEN OTHERS=＞y＜='X';
END CASE;
END PROCESS
END dataflow;